--
-- VHDL Architecture Fietscomputer_lib.fs_rst2LEDG.v
--
-- Created:
--          by - John Mooijekind.UNKNOWN (ZXP1)
--          at - 10:11:03 23-05-2011
--
-- using Mentor Graphics HDL Designer(TM) 2008.1b (Build 7)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;

ENTITY fs_rst2LEDG IS
  PORT(
  clr   : IN     STD_LOGIC;
  rst   : IN     STD_LOGIC;
  LEDG  : OUT    STD_LOGIC_VECTOR(8 DOWNTO 0)
  
  );
END ENTITY fs_rst2LEDG;

--
ARCHITECTURE v OF fs_rst2LEDG IS
BEGIN
  
  
  LEDG <= "011000000" WHEN rst = '1' ELSE
          "100010000" WHEN clr = '1' ELSE
          "000010000";
  
  
END ARCHITECTURE v;

